Design Verification Engineer - Verilog

Recruiter
ISL Recruitment
Location
Cheshire
Salary
40000.00 - 60000.00 GBP Annual + Benefits
Posted
22 May 2019
Closes
29 May 2019
Sector
Engineering
Contract Type
Permanent
Hours
Full Time

Role: Design Verification Engineer

Location: Commutable from - Central Manchester + 1hour

Salary: ??40,000-??60,000 (There is a senior and mid-level position available)

Key Skills: Verilog, Systems Verilog, SVA, UVM Verification, CPU/DSP Cores

Do you like the sound of career with a well-established company that values its employees and rewards them with progression?

Would you like to be part of a well-structured company, with clear project life cycles to work through within one of the most boundary pushing industries available?

I am helping manage the recruitment for an industry leading communications company working on space and satellite systems! With an international presence, we are growing the Manchester based engineering team immediately. I've kept the advert brief, with a lot more information available.

Day to Day Activity:

*Develop test strategies for verification stage of SoC, VLSI modems for the company
*Collaborate with device level teams and architects to help define verification requirements to get right first time
*Work with team to develop test benches and plan to meet metrics and coverage goals of the business
*Debug of test failures from simulations, work with team to identify and support the fix!

Required Experience from day 1:

*Creating complex verification environments using Verilog and System Verilog
*System Verilog Assertions (SVA)
*UVM Verification methodology
*Functional and Code coverage methods/techniques
*Constrained Random and Directed test cases for corner case bugs
*On chip interfaces: AXI, AHB, APB, OCP, etc
*On chip CPU and DSP cores: ARM, MIPS, CEVA, etc
*Expertise with Industry standard simulators and waveform viewers (Cadence, Mentor and Synopsys)
*Problem-solving and analytical skills
*Practical use of Scripting languages Tcl/Python/Perl etc and Experience with C/C++

This company are taking recruitment seriously, and we have processes set up to interview suitable engineers quickly and efficiently - please get in contact to discuss this role with me please contact Milo or email (see below)

From previous experience this position will be competitive and urgent action is recommended.

Key Skills: Verilog, Systems Verilog, SVA, UVM Verification, CPU/DSP Cores

ISL (Incite Solutions Ltd) is acting as an Employment Agency in relation to this vacancy.

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